2016-11-21 12:48:29 +01:00
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#include "ardusss7.h"
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#include <avr/io.h>
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#include <avr/interrupt.h>
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SSS7Wrapper SSS7;
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2016-11-26 20:14:37 +01:00
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void SSS7Wrapper::init() {
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2016-11-21 12:48:29 +01:00
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sss7_init();
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this->setupUart();
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this->setupTimer();
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}
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uint8_t SSS7Wrapper::canSend() {
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return sss7_can_send();
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}
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void SSS7Wrapper::send(uint8_t msg[SSS7_PAYLOAD_SIZE]) {
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return sss7_send(msg);
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}
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uint8_t SSS7Wrapper::sendFailed() {
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return sss7_send_failed();
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}
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uint8_t SSS7Wrapper::hasReceived() {
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return sss7_has_received();
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}
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void SSS7Wrapper::getReceived(uint8_t msg[SSS7_PAYLOAD_SIZE]) {
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sss7_get_received(msg);
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}
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void SSS7Wrapper::setupUart() {
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2016-12-25 21:39:33 +01:00
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UBRR0H = UBRR_VAL >> 8; // Setting baudrate
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UBRR0L = UBRR_VAL & 0xFF;
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2016-11-21 12:48:29 +01:00
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2016-12-25 21:39:33 +01:00
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UCSR0B = (1 << TXEN0) | (1 << RXEN0); // Enable TX and RX
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UCSR0C = (1 << UCSZ01) | (1 << UCSZ00); // Asynchronous 8N1
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2016-11-21 12:48:29 +01:00
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// flush UDR
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do
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{
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2016-12-25 21:39:33 +01:00
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UDR0;
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2016-11-21 12:48:29 +01:00
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}
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2016-12-25 21:39:33 +01:00
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while (UCSR0A & (1 << RXC0));
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2016-11-21 12:48:29 +01:00
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// reset tx and rx complete flags
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2016-12-25 21:39:33 +01:00
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UCSR0A = (1 << RXC0) | (1 << TXC0);
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2016-11-21 12:48:29 +01:00
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2016-12-25 21:39:33 +01:00
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UCSR0B |= (1 << TXCIE0) | (1 << RXCIE0); // enable tx and rx interrupts
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2016-11-21 12:48:29 +01:00
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}
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void uart_put_byte(uint8_t byte) {
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2016-12-25 21:39:33 +01:00
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UDR0 = byte;
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2016-11-21 12:48:29 +01:00
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}
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uint8_t uart_get_byte() {
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2016-12-25 21:39:33 +01:00
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return UDR0;
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2016-11-21 12:48:29 +01:00
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}
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2016-12-26 23:26:19 +01:00
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ISR(USART_RX_vect) {
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2016-11-21 12:48:29 +01:00
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sss7_process_rx();
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}
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2016-12-26 23:26:19 +01:00
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ISR(USART_TX_vect) {
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2016-11-21 12:48:29 +01:00
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sss7_process_tx();
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}
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2016-11-21 13:10:14 +01:00
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void SSS7Wrapper::setupTimer() {
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2016-12-25 21:39:33 +01:00
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TCCR1B = 0;
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TCNT1 = 65535 - 16000; //Preload for 16000 ticks to overflow
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2016-11-26 22:44:56 +01:00
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// Take the Timer by force ...
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2016-12-25 21:39:33 +01:00
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TCCR1A = 0;
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TCCR1B = (1 << CS10); // Prescaler 1
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TCCR1C = 0;
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2016-11-26 22:44:56 +01:00
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2016-12-25 21:39:33 +01:00
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TIMSK1 = (1 << TOIE1);
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2016-11-21 13:10:14 +01:00
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}
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2016-12-26 00:33:19 +01:00
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ISR(TIMER1_OVF_vect) {
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2016-12-25 21:39:33 +01:00
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TCNT1 = 65535 - 16000; //Preload for 16000 ticks to overflow
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2016-11-21 13:10:14 +01:00
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sss7_process_ticks(sss7_timeout_increment);
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}
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